1. Field of the Invention
The invention relates to flat panel displays. In particular, the invention relates to a process of manufacturing field emission displays.
2. Description of the Related Art
The Field Emission Displays (xe2x80x9cFEDxe2x80x9d) is a flat panel display type that may be able to compete with the liquid crystal display (LCD). FEDs have the advantages of being potentially lower in cost, low power consumers, having a better viewing angle, having higher brightness, having less smearing of fast moving video images, and being tolerant to greater temperature ranges than other display types.
Typically, a FED comprises a faceplate and a baseplate separated by spacers. A luminescent phosphor coating is applied to the inside surface of the faceplate to form phosphorescent pixel sites arranged in a matrix. Electrons from a cathode member bombard the coating in a pre-determined pattern to produce an image. The cathode member is formed by depositing micron-high sharp-tip cones thereon to form individual electron-emission sites or cathode tips which emit electrons to activate the corresponding pixels. In operation, a positive voltage (relative to the emitters) is applied to an extraction grid surrounding the emitters to produce an intense electrical field. This field is necessary for cold cathode emission. In some embodiments, the cathode member is attached to or integrally formed with the baseplate, and in other embodiments, the cathode member is attached to the faceplate and surrounded by a separate baseplate. In either case, the cathode member must be aligned with the faceplate so that the cathode tips are in opposed relation to the specific pixels which they are intended to activate.
A vacuum gap, ranging from a few tens of microns to many millimeters, separates the faceplate from the baseplate. Making the gap as small as possible lowers the extraction voltage required to accelerate the electrons from the cathode member on the baseplate to the phosphorescent coating on the faceplate which in turn reduces the cost of the driver electronics. The vacuum gap can be maintained by either a sealing member, a spacer or both. The sealing member and/or spacers maintain the required vacuum between the faceplate and baseplate (for example 10-6 Torr) and prevent the outside atmospheric pressure from collapsing them onto each other. Any degradation of the vacuum can result in a number of problems including the overall reduction in the working lifetime of the display. One of the most severe problems is nonuniform brightness of the display caused by contaminant gasses degrading the emitter tips, resulting in intermittent emissions. Thus, maintaining proper seal between the faceplate and baseplate is crucial to the proper operation of the display.
During the manufacture of the FED, the alignment of the cathode tips on the baseplate with their corresponding pixels on the faceplate must be maintained while the seal between the faceplate and the baseplate is formed. Maintaining the proper pixel alignment while forming the seal during assembly is a problematic task. In the prior art, once the faceplate and baseplate are aligned, temporary and permanent adhesives have been used to hold the faceplate and baseplate together in their aligned state while the seal between the two is being formed. Further, sealing typically occurs under a combination of high temperatures and high vacuum. However, internal cleanliness is critical. Thus, temporary attachment must therefor be accomplished with materials that do not outgas appreciably (unlike epoxy). Additionally, the application of the adhesive to the faceplate and baseplate necessarily requires an additional assembly step which increases assembly time and cost. Also, concerns over the long term stability of the permanent adhesives have made them less desirable to use. Further, temporary adhesives require yet another assembly step to remove the adhesive once the seal has been formed. Thus, there exists a need for a different manner of maintaining the alignment of the faceplate and the baseplate of a field emission display to enable the sealing process to be completed.
A process for fabricating a flat panel display having a faceplate and a baseplate comprises creating an electric field between the faceplate and the baseplate to temporarily attract the faceplate to the baseplate and attaching the baseplate and faceplate to each other while the electric field is present.
In accordance with one embodiment, a first portion of a capacitor is formed on the faceplate and a second portion of a capacitor is formed on the baseplate. The first and second portions of the capacitor are energized using opposite polarity voltages to create an electric field which produces an attractive force between the faceplate and baseplate. The baseplate and faceplate are then attached to each other while the attractive force is present. Preferably, when the baseplate and faceplate are attached to each other a seal is formed between the faceplate and the baseplate. Once attached, the first and second portions of the capacitor are de-energized to remove the attractive force between the faceplate and baseplate.
In accordance with one aspect of the present invention, the faceplate has a pixel matrix and the baseplate has a cathode member. When the first portion of the capacitor is formed on the faceplate, the first portion of the capacitor is aligned with the pixel matrix. When the second portion of the capacitor is formed on the baseplate, the second portion of the capacitor is aligned with the cathode member. Therefore, when the first and second portions of the capacitor are energized and the attractive force is created between the first and second portions of the capacitor, the pixel matrix and the cathode member are automatically aligned with each other.
In one embodiment, at least one capacitor is formed between the faceplate and baseplate. In another embodiment, at least two capacitors are formed between the faceplate and baseplate with the at least two capacitors located on opposite corners of the faceplate and baseplate. In a preferred embodiment, four capacitors are formed between the faceplate and baseplate, one on each corner thereof.
In another embodiment, the process for fabricating a flat panel display comprises forming a plurality of interdigitated conductors on the baseplate. A first plurality of the conductors are energized to a first polarity voltage and a second plurality of the conductors are energized to a second polarity voltage, thereby creating an electric field above the baseplate. The faceplate is then placed in proximity to the baseplate while the electric field is present. Electrostatic force from the electric filed pulls the faceplate and adheres it to the baseplate. The baseplate and faceplate are attached to each other while the electric field is present. After the baseplate and faceplate are attached to each other, the first and second plurality of conductors are de-energized thereby dissipating the electric field. In an alternate embodiment, the array of conductors are formed on the faceplate and the baseplate is attracted to the faceplate when the conductors are energized to opposite polarity voltages.
In accordance with another aspect of the present invention, a flat panel display comprising a faceplate and a baseplate, further comprises a capacitor having first and second portions thereof. The first portion of the capacitor is formed on the faceplate and the second portion of the capacitor is formed on the baseplate. The faceplate comprises a pixel matrix and the first portion of the capacitor is preferably aligned with the pixel matrix. The baseplate further comprises a cathode member and the second portion of the capacitor is preferably aligned with the cathode member.
In one embodiment, the first portion of the capacitor comprises a metal layer and a dielectric material layer and the second portion of the capacitor comprises a metal layer. In another embodiment, the second portion of the capacitor further comprises an oxide layer. In still another embodiment, the first portion of the capacitor comprises a metal layer and the second portion of the capacitor comprises a metal layer and a dielectric material layer.